module is_mahb2sahb
    (
    input wire          hclk,
    input wire          hrst_n,
    //来自tee总线上的s10端口信号
    input wire   [31:0] hmain1_mahb2sahb_haddr,
    input wire   [2 :0] hmain1_mahb2sahb_hburst,
    input wire   [3 :0] hmain1_mahb2sahb_hprot,
    input wire   [2 :0] hmain1_mahb2sahb_hsize,
    input wire   [1 :0] hmain1_mahb2sahb_htrans,
    input wire   [31:0] hmain1_mahb2sahb_hwdata,
    input wire          hmain1_mahb2sahb_hwrite,
    input wire          hmain1_mahb2sahb_hsel,
    output wire  [1 :0] mahb2sahb_hmain1_hresp,
    output wire         mahb2sahb_hmain1_hready,
    output wire  [31:0] mahb2sahb_hmain1_hrdata,
    //去往ree总线上的m4端口信号
    output wire  [31:0] mahb2sahb_ree_bus_haddr,
    output wire  [2 :0] mahb2sahb_ree_bus_hburst,
    output wire  [3 :0] mahb2sahb_ree_bus_hprot,
    output wire  [2 :0] mahb2sahb_ree_bus_hsize,
    output wire  [1 :0] mahb2sahb_ree_bus_htrans,
    output wire  [31:0] mahb2sahb_ree_bus_hwdata,
    output wire         mahb2sahb_ree_bus_hwrite,
    input wire          ree_bus_mahb2sahb_hgrant,
    input wire   [31:0] ree_bus_mahb2sahb_hrdata,
    input wire          ree_bus_mahb2sahb_hready,
    input wire   [1 :0] ree_bus_mahb2sahb_hresp
    );

assign mahb2sahb_ree_bus_haddr        = hmain1_mahb2sahb_haddr;             //驱动端口信号
assign mahb2sahb_ree_bus_hburst       = hmain1_mahb2sahb_hburst;            //驱动端口信号
assign mahb2sahb_ree_bus_hprot        = hmain1_mahb2sahb_hprot;             //驱动端口信号
assign mahb2sahb_ree_bus_hsize        = hmain1_mahb2sahb_hsize;             //驱动端口信号
assign mahb2sahb_ree_bus_htrans       = hmain1_mahb2sahb_htrans;            //驱动端口信号
assign mahb2sahb_ree_bus_hwdata       = hmain1_mahb2sahb_hwdata;            //驱动端口信号
assign mahb2sahb_ree_bus_hwrite       = hmain1_mahb2sahb_hwrite;            //驱动端口信号

assign mahb2sahb_hmain1_hresp         = ree_bus_mahb2sahb_hresp;              //驱动端口信号
assign mahb2sahb_hmain1_hready        = ree_bus_mahb2sahb_hready;
assign mahb2sahb_hmain1_hrdata        = ree_bus_mahb2sahb_hrdata;             //驱动端口信号

endmodule

